DV - Digital Verification Engineer (Senior levels - Staff +)

Eliyan's mission is to revolutionize chiplet connectivity technologies by challenging the status quo to unleash the ultimate performance of smart systems of the future.

Location: Vancouver, BC
Company size: 20–50
Posted: 1y ago
Via: Lever

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DV - Digital Verification Engineer (Senior levels - Staff +) · Eliyan

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Job title: DV - Digital Verification Engineer (Senior levels - Staff +)
Job location: Vancouver, BC OR Bay Area, CA
Job listing URL: https://jobs.lever.co/eliyan/d3c80ca3-833e-4e92-a656-5a36514b43c5
Job description: Join the leading chiplet startup! As an Eliyan staff digital verification engineer, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow’s chiplet based systems with best-in-class power, area, manufacturability, and design flexibility. You will be developing state-of-the-art testbenches and unit/chip level test cases for best-in-class PHYs and Controllers. You will work with a cross-functional team of experts that operate from first principles, innovate and push the envelope to create high-volume and high-performance manufacturable products. We offer a fun work environment with excellent benefits.
Key Responsibilities:
Develop and execute verification plans for connectivity IPs and Chiplets

Create and maintain SystemVerilog/UVM-based verification environments

Write and debug SystemVerilog/UVM compliant test cases for block and chip level

Maintain a regression environment for enabling design CI/CD pipelines

Collaborate with design engineers to ensure design quality with continuous microarchitecture, test-plan, and coverage reviews

Develop, maintain, and track various test plan items and progress towards RTL freeze

Stay up to date with industry trends, emerging technologies and progress in standards’ bodies

Ensure IP compliance with Ethernet standards (IEEE 802.3)

Integration 3rd party VIPs and coordinate feature/bug tracking requests

Perform in the capacity of a technical leader for junior verification engineers

Create, improve, maintain DPI based FW simulation environments

Create, improve, maintain GLS environments for functional and power simulations
Qualifications:
Masters or Ph.D in Electrical Engineering and related fields with 6+ years of experience

Hands on experience in verification of serial transmission protocols and products (preferably in retimer, gearbox, Ethernet PMA/PCS logic)

Strong expertise in UVM, test environment and assertion coding with SystemVerilog

Proficiency in 3 rd party tools for regression management and coverage analysis

3+ experience working on Ethernet 802.3 standards’ clauses related to 100G, 200G, 400G, 800G; Auto-Negotiation and Link Training

Knowledge of DRAM Controllers/PHYs and HBM Memory a plus

Strong bias for innovations across all aspects of digital verification including automation of mundane activities and methods for quality improvement

Experience in verifying 3 rd party mixed signal IPs as well as integration of VIPs

Proven track record of being part of a start-up like environment