SECTION I · THE BRIEF
Brief #53700Updated 30 JUL 2024SAN FRANCISCOLeverSAN FRANCISCO
Employbl Dossier

Sensor Package Design Engineer

San Francisco, Hardware, LASERS

Location
San Francisco
Company size
292–292
Posted
1y ago
Via
Lever
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  • 01Comp band & equity packageLocked
  • 02Seniority & experience requirementsLocked
  • 03Interview process & rubricLocked
  • 04Hiring manager & team contextLocked
  • 05Growth trajectory in this roleLocked
  • 06Offer & decision timelineLocked

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Sensor Package Design Engineer - Ouster

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Job Title
Sensor Package Design Engineer
Job Location
San Francisco
Job Description
At Ouster, we build sensors and tools for engineers, roboticists, and researchers, so they can make the world safer and more efficient. We've transformed LIDAR from an analog device with thousands of components to an elegant digital device powered by one chip-scale laser array and one CMOS sensor. The result is a full range of high-resolution LIDAR sensors that deliver superior imaging at a dramatically lower price. Our advanced sensor hardware and vision algorithms are used in autonomous cars, drones and many other applications. If you’re motivated by solving big problems, we’re hiring key roles across the company and need your help!

We are looking for a Sensor Packaging Development and Production Engineer to design and develop our IC packaging solutions. We are seeking an adaptable, well-organized engineer who can work between hardware, systems, IC and operations to drive our packaging development. The role is San Francisco based and will include some travel.
RESPONSIBILITIES:
  • Design microelectronic assembly processes for automotive-grade receiver and transmitter packages / modules from wafer fab to package integration
  • Define specifications for custom IC package designs and chip carriers to meet product and qualification requirements. Work with external partners to realize those parts
  • Plan and execute process optimization and characterization, design validation, failure analysis, and sample builds for package development and automotive qualification
  • Lead yield analysis and drive improvement/corrective actions for silicon process and microelectronic assembly
  • Collaborate with external manufacturing partners to develop new packaging processes and prototypes to meet IC and system specifications.
  • Manage vendors, including sourcing, vetting, quoting, design for manufacturing (DFM), and low-volume order placement of diverse components such as substrates, epoxies, coated glass, PCBAs, and tooling.
  • Drive mass production readiness with multiple engineering and operation teams
  • BASIC QUALIFICATIONS:
  • 5+ years in Semiconductor Package/Process Development or 2+ years with a relevant masters degree.
  • Experience with multi-layer ceramic, CMOS image sensor, BGA packages, and organic substrates
  • Experience in wafer level processing (dielectric thin film deposition, RIE silicon processing, wafer-to-wafer bonding, spin coat/lift-off processing, wafer dice and test)
  • Experience in automated micro electronic and photonic assembly processes (wafer inspection, high accuracy epoxy/solder die attach, wire bonding, vision inspection, glob top/underfill dispense)
  • Working knowledge of Failure Analysis tools such as X-ray, 3D interferometry, DIC microscopy, SEM, cross-section, destructive testing, etc.
  • Understanding of CMOS image sensor sensor architecture and operation is preferred
  • BONUS QUALIFICATIONS:
  • Bachelor's and/or Master's degree in Electrical or Mechanical Engineering
  • Experience with optical systems
  • Experience with ATE package test environment
  • Experience with statistical analysis for volume production processes
  • AEC-Q100 or related automotive qualification experience
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    Ouster Headquarters Location

    San Francisco, CA

    View company profile

    Ouster Company Size

    Between 292 - 292 employees

    Ouster Founded Year

    2015

    Ouster Total Amount Raised

    $282,000,000

    Ouster Funding Rounds

    View funding details
    • Post Ipo Debt

      $50,000,000 USD

    • Post Ipo Debt

      $50,000,000 USD

    • IPO

      $0

    • Post Ipo Equity

      $100,000,000 USD

    • Post Ipo Equity

      $100,000,000 USD

    • IPO

      $0

    • Series B

      $42,000,000 USD

    • Series B

      $42,000,000 USD

    • Debt Financing

      $20,000,000 USD

    • Series Unknown

      $40,000,000 USD

    • Series Unknown

      $40,000,000 USD

    • Debt Financing

      $20,000,000 USD

    • Series A

      $27,000,000 USD

    • Series A

      $27,000,000 USD

    • Seed

      $3,000,000 USD

    • Seed

      $3,000,000 USD