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Principal Product Applications Engineer - Astera Labs

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Job Title
Principal Product Applications Engineer
Job Location
Shanghai, China
Job Description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of cloud and AI infrastructure. Our Intelligent Connectivity Platform integrates PCIe, CXL and Ethernet semiconductor-based solutions based on a software-defined architecture that is both scalable and customizable. Inspired by trusted partnerships with hyperscalers and the data center ecosystem, we are an innovation leader with products that are flexible, interoperable, and reliable. We are headquartered in the heart of California’s Silicon Valley, with R&D centers and offices in Texas, Taiwan, China, Canada, and Israel. 

As an Astera Labs Product Applications Engineer, you will be part of a team that supports design-in of Astera Labs’ portfolio of connectivity products by the world’s leading cloud service providers and server and network OEMs. In this role, you will need to provide technical guidance to customers to overcome design challenges, generate collateral for existing and new products, and drive innovation by providing insightful feedback to other internal teams to continuously improve products and processes. You will investigate and duplicate issues reported by customers, and drive critical issues to resolution. There are opportunities to support key customers directly, and also to dive deep in the lab to address the challenges associated with leading edge semiconductor products.

Basic Qualifications

  • Strong academic and technical background in electrical, electronics, or computer engineering or a closely related field. At a minimum, an engineering bachelor’s degree is required. A master’s degree is preferred.
  • A minimum of 12 years’ experience working with cloud service providers or server or network OEM customers to design in complex SoC/silicon products for server, storage, and/or networking applications.
  • Entrepreneurial spirit, open-minded approach, and can-do attitude. Think and act with the customer in mind!

Required Experience

  • Silicon/system bring-up and debug experience in customer systems.
  • Strong knowledge of embedded FW development and in-system debug
  • Firmware development with C-language, scripting with Python or other equivalent programming languages.
  • Strong knowledge of PCIe protocol, including LTSSM, EQ, DMA, etc.
  • Strong knowledge of NRZ/PAM4 SerDes level debugging (TX/RX Equalization) in PCIe, Ethernet (25G and above), etc.
  • Firsthand experience with lab equipment including traffic generators, analyzers, and high-speed oscilloscopes.
  • Broad knowledge of NRZ/PAM4 SerDes-based protocols such as PCIe or Ethernet (25G and above).
  • Understanding of Data Center systems such as servers, compute nodes, JBOGs/JBODs, and networking switches/routers/interconnects, etc.
  • Technical writing skills and the ability to generate clear, precise documentation including datasheets, application notes, and similar guides for both internal audiences and customers.

Preferred Experience

  • Broad knowledge of signal processing and ECC coding for communications
  • Device driver development
  • Development/support for PCIe or Ethernet switch products
  • Working with silicon characterization/validation teams to ensure desired device performance is readily achievable in customer systems.
  • Knowledge of simulation/modeling, schematic capture, and PCB layout tools from Cadence, Altium and others.
  • Knowledge of simulation tools such as Keysight ADS, SiSoft QCD, and others, for IBIS-AMI analysis.
  • A strong background in high-speed board design and techniques for preserving signal integrity.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

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Astera Labs Headquarters Location

Santa Clara, CA

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Astera Labs Company Size

Between 440 - 440 employees

Astera Labs Founded Year

2017

Astera Labs Total Amount Raised

$206,350,000

Astera Labs Funding Rounds

View funding details
  • IPO

    $0

  • Series D

    $150,000,000 USD

  • Series C

    $50,000,000 USD

  • Series Unknown

    $6,350,000 USD

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