TECHNOLOGY · FRAMEWORKS & LIBRARIES

Universal Verification Methodology

Standardized SystemVerilog-based framework for functional verification of hardware designs, widely adopted in chip development.

Open roles mentioning it
115
Companies hiring for it
40
Remote share
1%
WHO'S HIRING

Companies with open roles mentioning Universal Verification Methodology

SpaceX12 open rolesTenstorrent8 open rolesMatX7 open rolesEtched.ai6 open rolesLumilens6 open rolesAstera Labs6 open rolesNormal Computing5 open rolesVelaura AI5 open rolesBaya Systems5 open rolesEliyan5 open rolesAST SpaceMobile4 open rolesRocket Lab3 open roles
APPEARS ALONGSIDE

Technologies mentioned in the same job posts

SystemVerilog×82Python×53Verilog×36C++×34Tcl×14Xilinx×14Microsoft Fabric×10Change Data Capture×9Linux×8MATLAB×6
COMMON ROLES

Job titles that ask for Universal Verification Methodology

  • Design Verification Engineer7
  • Sr. Asic Design Verification Engineer (Silicon Engineering)4
  • Design Verification Engineer (Silicon Engineering)4
  • Hardware Verification Engineer4
  • Principal Design Verification Engineer (Silicon Engineering)4
  • Senior Design Verification Engineer3
  • Digital Verification Engineer2
  • Asic Design Verification Engineer2
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