Physical Design 

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe®, CXL®, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com.  

Basic qualifications:

• Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE / Computer is required, and a Master’s degree is preferred.
• ≥8 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision. 
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!

Required experience:

• Hands-on and thorough knowledge of synthesis, place and route, CTS, extraction timing analysis/STA, Physical Verification and other backend tools and methodologies for technologies 16nm or less, preferably 7nm or less.
• Proven expertise in synthesis, timing closure and formal verification (equivalence) at the block and full-chip level.
• Full chip or block level ownership from architecture to GDSII, driving multiple complex designs to production.
• Experience with Cadence and/or Synopsys physical design tools/flows.
• Familiarity and working knowledge of System Verilog/Verilog.
• Experience with DFT tools and techniques.
• Experience in working with IP vendors for both RTL and hard-mac blocks.
• Good scripting skills in python or Perl

Preferred :

• Good knowledge of design for test (DFT), stuck-at and transition scan test insertion.
• Familiarity with DFT test coverage and debug.
• Familiarity with ECO methodologies and tools.