Role Overview
As a Staff/Sr. Staff Physical Verification Engineer at Velaura AI, you will own block-level and full-chip physical verification and signoff for next-generation AI and high-performance computing silicon. You will drive physical verification from block-level implementation through full-chip integration and final tape-out, working on complex SoC designs targeting advanced process technologies.
This is a highly hands-on technical role requiring deep expertise in DRC, LVS, ERC, PERC, antenna, ESD/EOS, and reliability verification, along with the ability to identify root causes and implement physical fixes directly in Cadence Innovus and/or Synopsys Fusion Compiler.
You will work closely with Physical Design, Analog/Mixed-Signal, STA, Power Integrity, Reliability, I/O, and CAD teams to drive signoff convergence, establish robust PV methodologies, and achieve first-time-right silicon.
Responsibilities
● Own block-level and full-chip physical verification signoff, including DRC, LVS, ERC, PERC, antenna, ESD/EOS, and related reliability checks for complex ASIC/SoC designs.
● Drive tape-out readiness and signoff closure through violation triage, root-cause analysis, waiver management, schedule tracking, and convergence to zero or signoff-acceptable violations.
● Execute and debug physical verification using industry-standard tools such as Siemens Calibre and Synopsys IC Validator (ICV), including complex connectivity, device-recognition, hierarchy, and advanced-node rule issues.
● Correlate Calibre/ICV results with Cadence Innovus and/or Synopsys Fusion Compiler implementation databases and drive physical fixes through iterative verification to closure.
● Perform hands-on physical implementation and ECO changes, including routing and via edits, metal-shape modifications, cell movement, filler/decap/endcap updates, power-grid modifications, and other layout changes required for signoff.
● Define, customize, and enhance PERC and reliability verification flows covering ESD, EOS, latch-up, point-to-point resistance, current-density constraints, and high-current paths.
● Develop Tcl and Python/Perl/Unix shell automation for violation analysis, implementation database queries, physical ECOs, PV execution, and signoff reporting.
● Drive PV closure for advanced FinFET and GAA technologies, including restrictive spacing, coloring, cut-mask, EUV/multi-patterning, and other advanced-node-specific requirements.
● Influence floorplanning, power-grid planning, and implementation methodology from a physical verification perspective to minimize downstream iterations and late-stage signoff violations.
● Support hierarchical and full-chip PV methodologies for digital-on-top, mixed-signal, and multi-voltage SoCs, including IP integration and boundary/interface verification.
● Partner with Physical Design, STA, Power Integrity, Analog, and Reliability teams to ensure PV-driven changes preserve timing, congestion, routability, signal integrity, power integrity, reliability, and design functionality.
● Develop and optimize physical verification flows for runtime, scalability, robustness, and ease of use across block and full-chip designs.
● Partner with CAD teams, foundries, and EDA vendors to qualify technology nodes and rule decks, resolve complex PV/reliability issues, and improve verification and signoff methodologies.
● Drive density, metal-fill, DFM/DFY, and pattern-matching verification while ensuring associated changes do not introduce timing, reliability, or physical verification regressions.
● Mentor engineers on physical verification methodology, advanced-node debugging, root-cause analysis, implementation fixes, and tape-out signoff best practices.
Required Qualifications
● Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, VLSI, Microelectronics, or a related field.
● Typically 8+ years of relevant experience in physical verification for complex ASIC/SoC designs, with multiple successful production tape-outs.
● Proven experience owning block-level and/or full-chip physical verification signoff for complex ASIC/SoC designs.
● Strong hands-on experience with DRC and LVS signoff, with experience or strong exposure to PERC and reliability verification.
● Experience with advanced FinFET and/or GAA technologies, including at least one production tape-out at an advanced process node.
● Strong hands-on expertise with Siemens Calibre and/or Synopsys ICV, including debugging complex DRC, LVS, antenna, connectivity, and advanced-node physical verification issues.
● Demonstrated ability to perform manual and scripted physical implementation/ECO changes in Cadence Innovus and/or Synopsys Fusion Compiler.
● Experience correlating physical verification results with implementation databases and driving physical fixes through iterative verification to signoff closure.
● Strong scripting skills in Tcl and at least one of Python, Perl, or Unix shell for PV automation, implementation database queries, ECOs, and flow development.
● Strong understanding of how PV-driven physical changes impact timing, congestion, routability, signal integrity, power integrity, reliability, and overall design closure.
● Strong debugging, problem-solving, and root-cause-analysis skills, with the ability to independently drive complex signoff issues to closure.
● Excellent communication skills and the ability to work effectively across Physical Design, Analog, STA, CAD, Reliability, Foundry, and EDA teams.
Preferred Qualifications
● Hands-on experience with PERC-based reliability verification for ESD, EOS, latch-up, point-to-point resistance, current-density constraints, and high-current paths, including flow setup, customization, debugging, and definition of signoff criteria.
● Experience with Cadence Virtuoso integration with Calibre/ICV for DRC, LVS, and PERC verification in analog or mixed-signal environments.
● Experience driving hierarchical and full-chip PV signoff for digital-on-top, mixed-signal, and/or multi-voltage SoCs.
● Experience with DFM/DFY, density and metal-fill strategies, pattern-matching verification, and advanced-node manufacturing checks.
● Experience qualifying foundry rule decks, new technology nodes, verification methodologies, and signoff flows.
● Experience working directly with foundries and EDA vendors on complex rule interpretation, deck, methodology, and signoff issues.
● Experience working in a fast-paced or early-stage semiconductor environment.
