Role Overview
We are looking for talented Design Verification Engineers to help verify and deliver Velaura's next generation Physical AI SoC. You will work closely with architects, RTL engineers, software engineers and system teams to establish confidence in the correctness, performance, reliability and safety of the design, from individual RTL blocks through complete hardware and software systems running real workloads.
This role focuses on our AI acceleration units. We are designing custom compute engines from scratch to deliver industry leading inference performance at best in class energy efficiency, and every gain has to come inside a tight power envelope. You will own verification of the hardware that makes those numbers real, where correctness means numerical behavior as much as protocol.
Responsibilities
Own verification of Velaura's custom AI acceleration units including matrix and vector compute engines.
Work with architects to understand the intent behind a newly designed microarchitecture and turn it into detailed test and coverage plans, including the criteria that define correctness for numerical hardware.
Build verification environments using SystemVerilog, UVM, C and C++, with stimulus, checkers, assertions, trackers and coverage that stay portable across block and subsystem environments.
Develop reference models for GEMM and GEMV operations and compare hardware results against them.
Verify accelerator data flow including operand staging, tiling, accumulation and result writeback.
Verify precision, rounding and quantization behavior against the architecture specification.
Verify throughput, latency, utilization and performance per watt against aggressive targets under representative LLM and vision workloads.
Execute regressions through design and environment bring up, track progress using bug and coverage metrics, and support emulation and pre silicon bring up with the compiler and runtime teams.
Required Qualifications
8 or more years verifying high performance compute or complex digital designs.
High level understanding of LLMs including transformer structure and inference data flow.
Knowledge of GEMM and GEMV operations and how they map onto hardware.
Experience with SystemVerilog, UVM, C and C++, assertions and coverage driven verification.
Experience building or using reference models in C, C++ or Python.
Understanding of numerical formats and precision tradeoffs such as FP16, BF16, FP8 and INT8.
Experience owning a block or unit of a design independently from test plan through coverage closure, including debug of complex failures.
BS or higher in Computer Engineering, Electrical Engineering or Computer Science.
Preferred Qualifications
Prior experience porting LLM or neural network models to RTL and verifying them.
Experience verifying a custom accelerator developed from scratch rather than an integrated third party IP.
Familiarity with systolic arrays, tensor cores, attention, KV cache or mixture of experts hardware.
Experience with PyTorch, ONNX or compiler and runtime stacks for accelerators.
Experience with formal verification, gate level simulation or silicon bring up.
Exposure to performance modeling, power analysis, profiling and workload characterization.
Familiarity with robotics, drones, autonomous vehicles or edge AI systems.
Experience using AI assisted verification workflows to improve productivity and coverage.
