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ASIC/SOC Silicon Physical Design Engineer - MatX

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Job Title
ASIC/SOC Silicon Physical Design Engineer
Job Location
Mountain View, CA
Job Description

MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking silicon physical design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates for these roles will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management. High-speed connectivity and other key technologies in leading-edge process nodes.

Responsibilities include:

  • Contribute to MatX’s silicon design and physical design methodology with a scalable solution across blocks, subsystems, fullchip designs from RTL to GDS
  • Own entire subsystem or subsets and/or chip-level physical design deliverables including but not limited to: floor-planning, placement, clock insertion, routing, optimizations, timing closure analysis, physical verification closure, electrical analysis, etc.
  • Plan and drive intermediate and sign-off reviews as well as execution progress reporting based on key PPA metrics-tracking towards various silicon milestones including design freeze and tapeout
  • Work closely with the design, DFT and other physical design co-owners of the subsystem/block in question and deliver best-in-class performance-power-area results
  • Work with design services partners and other critical third-party vendors and partners on planning and executing block-level and chip-level closure for blocks you own and oversee

Requirements:

  • RTL-to-silicon experience in driving physical design for subsystems and/or top-level functions with ASICs and SOCs from early RTL design and netlist to production silicon 
  • Production-proven experience with Floorplanning, place and route, clock tree insertion and analysis, timing analysis, physical verification, electrical sign-off and related areas to produce tapeout ready GDS for large physical blocks and/or top-level
  • Project experience in collaborating with design, verification and DFT teams to structure and partition the design optimally for PPA and sign-off 
  • Experience in working with a third-party design services partner and taking subsystems and/or top-level from initial floor plan to sign-off and tapeout is a plus

Compensation: The US base salary for this full-time position is $120,000 - $400,000 + equity + benefits

As part of our dedication to the diversity of our team and our focus on creating an inviting and inclusive work experience, MatX is committed to a policy of Equal Employment Opportunity and will not discriminate against an applicant or employee on the basis of race, color, religion, creed, national origin or ancestry, sex, gender, gender identity, gender expression, sexual orientation, age, physical or mental disability, medical condition, marital/domestic partner status, military and veteran status, genetic information or any other legally recognized protected basis under federal, state or local laws, regulations or ordinances.

All candidates must be authorized to work in the United States and work from our offices in Mountain View Tuesdays-Thursdays.

This position requires access to information that is subject to U.S. export controls. This offer of employment is contingent upon the applicants capacity to perform job functions in compliance with U.S. export control laws without obtaining a license from U.S. export control authorities.

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MatX Headquarters Location

Mountain View, CA

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MatX Company Size

Between 10 - 50 employees

MatX Founded Year

2022

MatX Total Amount Raised

$24,908,676

MatX Funding Rounds

View funding details
  • Undisclosed

    $24,908,675 USD