About the Role

We are building a world-class SerDes engineering team to enable next-generation connectivity for AI data centers and high-performance computing.

We are seeking a highly accomplished Senior Principal Engineer to lead the design and development of advanced SerDes transmitter circuits. This role will drive key transmitter technologies spanning clock generation and distribution, high-speed DACs, output drivers, and innovative circuit techniques for extending bandwidth and improving power efficiency.

The ideal candidate combines deep expertise in high-speed analog and mixed-signal circuit design with hands-on experience in advanced transmitter architectures, time-interleaved DACs, high-speed clocking, and electromagnetic analysis. You will own critical design blocks from architecture and circuit development through layout collaboration, tape-out, and silicon validation, working closely with cross-functional teams to deliver leading-edge high-speed interconnect technology.

Responsibilities:

• Transmitter Design Leadership: Lead the architecture, design, and implementation of high-speed SerDes transmitter circuits targeting the next-generation high-speed interconnects, with a focus on performance, power efficiency, and silicon robustness.
• Clocking Architecture: Drive transmitter clock generation, distribution, and timing optimization, including multiphase clocking, phase alignment, jitter management, and clock-to-data timing.
• High-Speed DAC Development: Lead the design and optimization of high-speed DACs, including time-interleaved architectures, high-speed switching networks, linearity optimization, and power-efficient implementations.
• DAC Calibration: Develop and optimize calibration techniques for high-speed time-interleaved DACs, addressing timing skew, gain and offset mismatch, nonlinearities, interleaving spurs, and process-voltage-temperature variations.
• Output Driver Design: Lead the design of high-speed output drivers using both current-mode and voltage-mode architectures, optimizing output swing, impedance matching, linearity, power consumption, and signal integrity.
• Bandwidth Extension Techniques: Develop advanced circuit techniques using passive elements and networks—including inductive peaking, impedance shaping, and other bandwidth-extension methods—to achieve the required high-frequency performance.
• Electromagnetic Analysis: Apply electromagnetic simulation and extraction tools, such as Cadence EMX, Ansys HFSS, or other EM tools, to analyze and optimize passive structures, interconnects, coupling, and high-frequency circuit behavior.
• Cross-Functional Integration: Collaborate with receiver, clocking, AMS layout, package, signal integrity, and silicon validation teams to optimize end-to-end link performance.
• Silicon Execution: Drive circuit simulations, design reviews, physical implementation, tape-out readiness, silicon characterization, and performance correlation to ensure successful product delivery.
• Technical Mentorship: Provide technical guidance to engineers, establish design best practices, and help raise the technical bar across the SerDes transmitter organization.

Qualifications:

• MS or PhD in Electrical Engineering or a related field, with substantial experience in high-speed analog and mixed-signal IC design.
• Strong hands-on experience designing high-speed SerDes transmitters or comparable high-performance transmit circuits.
• Demonstrated expertise in one or more of the following areas: transmitter clocking, high-speed DACs, output drivers, or advanced transmitter architectures.
• Strong understanding of high-speed circuit design principles, including bandwidth limitations, parasitic effects, jitter, noise, impedance matching, signal integrity, and power optimization.
• Experience with advanced CMOS process technologies and the challenges of implementing high-speed circuits in scaled technology nodes.
• Proficiency in circuit simulation, design optimization, and silicon debug and characterization.
• Experience collaborating with custom layout engineers and using extracted parasitics and electromagnetic simulation results to guide circuit design.
• Proven ability to lead complex technical projects, make sound engineering trade-offs, and deliver high-quality silicon.

Preferred Qualifications:

• Direct experience developing 100+G-per-lane SerDes transmitters.
• Deep expertise in time-interleaved DAC architectures and calibration techniques for high-speed transmitters.
• Experience with both current-mode and voltage-mode output driver architectures, including their trade-offs in bandwidth, linearity, output swing, power, and termination.
• Strong understanding of passive circuit design for bandwidth extension, including inductors, transformers, transmission lines, resonant networks, and impedance-shaping techniques.
• Hands-on proficiency with electromagnetic simulation and extraction tools such as Cadence EMX, Ansys HFSS, or other EM tools, including PeakView where applicable.
• Experience optimizing clock distribution, multiphase clock generation, and sampling or switching-clock quality for high-speed mixed-signal systems.
• Experience with advanced-node CMOS technologies, high-density integration, and demanding package and channel environments.
• A track record of successful silicon delivery, technical innovation, patents, or contributions to leading-edge high-speed connectivity products.