About the Role

We are building a world-class SerDes engineering organization to enable next-generation, ultra-high-speed connectivity for AI data centers and high-performance computing.

We are seeking an experienced Senior Director of SerDes Engineering to establish, lead, and scale our engineering team across design centers. This is a strategic leadership role combining deep technical expertise in advanced SerDes development with organizational leadership, talent development, and cross-site engineering execution.

The successful candidate will build a high-performing team responsible for developing critical SerDes foundation IP and key circuit modules that enable our next-generation connectivity solutions. The team will have meaningful technical ownership, working closely with engineering leadership and design teams across locations to define architectures, develop critical IP, and deliver production-quality silicon.

We are particularly interested in leaders with strong experience in high-speed SerDes and foundation IP design who can lead and scale a collaborative, high-performance design center.

Responsibilities:

• Design Center Leadership: Establish and lead our SerDes engineering Bangalore design center, including organizational planning, hiring, resource allocation, engineering processes, and long-term capability development.
• Technical Leadership: Drive the development of advanced SerDes technologies for 100+G-per-lane and next-generation high-speed connectivity, with particular emphasis on receiver and clocking technologies.
• Foundation IP Ownership: Build and lead teams responsible for critical analog and mixed-signal foundation IP, including high-speed circuit building blocks, clocking circuits, receiver components, bandgap, LDO and other reusable technologies.
• Critical Module Development: Establish technical ownership of key SerDes modules, driving architecture, circuit design, implementation, verification, and silicon validation in close collaboration with the global engineering organization.
• Talent Acquisition and Development: Recruit exceptional engineering talent across experience levels, develop technical leaders, establish mentorship programs, and build a sustainable pipeline of future engineering talent.
• Engineering Excellence: Establish rigorous design methodologies, technical review processes, implementation standards, and quality practices to ensure high-quality, predictable silicon delivery.
• Cross-Site Collaboration: Build effective working relationships with engineering teams across locations, ensuring seamless technical communication, clear ownership boundaries, efficient decision-making, and alignment on project priorities.
• Execution and Delivery: Own engineering plans, schedules, resource commitments, and technical milestones for the organization, ensuring delivery of critical IP and design modules to support overall product objectives.
• Technical Culture: Foster a culture of technical depth, accountability, collaboration, and continuous improvement, empowering engineers to take ownership of complex design challenges.
• Organizational Scaling: Develop a long-term strategy for expanding the design center's technical scope, engineering capacity, and leadership capabilities as the company grows.

Qualifications:

• MS or PhD in Electrical Engineering or a related field.
• Extensive experience in high-speed SerDes or PHY development, with demonstrated technical leadership in complex analog and mixed-signal IC design.
• Direct experience with 100+G SerDes development or closely related next-generation high-speed connectivity technologies.
• Strong understanding of SerDes architecture and implementation, ideally with substantial experience in receiver, clocking, or other critical analog/mixed-signal subsystems.
• Proven experience building, managing, and scaling semiconductor engineering teams, including recruiting, mentoring, performance management, and leadership development.
• Demonstrated ability to lead complex silicon development programs from architecture and circuit design through tape-out and silicon validation.
• Experience establishing engineering processes, technical review mechanisms, and organizational practices that support high-quality execution at scale.
• Excellent communication and collaboration skills, with the ability to work effectively across geographically distributed engineering organizations.
• Strong execution skills and the ability to balance technical depth, organizational development, and program delivery.

Preferred Qualifications

• Experience leading engineering teams responsible for reusable foundation IP and multiple critical analog or mixed-signal design modules.
• Experience establishing or significantly scaling a semiconductor design center.
• A strong track record of recruiting senior engineers and developing technical leaders who can independently own complex design blocks.
• Experience with advanced CMOS process technologies, high-performance analog layout, parasitic extraction, and silicon characterization.
• Familiarity with advanced packaging, high-bandwidth die-to-die interfaces, and demanding AI data center connectivity requirements.
• Experience managing global engineering teams and coordinating complex development programs across multiple sites.
• Demonstrated success building an engineering organization that delivers meaningful technical innovation and measurable product results.