About the Role

Upscale AI is developing next-generation SerDes technology to enable the bandwidth, power efficiency, and scalability required by future AI infrastructure. We are seeking exceptional analog and mixed-signal design engineers to drive the development of complex, high-performance circuits and help shape the technical direction of our SerDes platform.

As a Senior Principal / Distinguished Engineer, you will lead technically challenging design efforts, influence circuit and subsystem architecture, and drive critical design decisions across multiple engineering disciplines. You will bring deep circuit expertise, strong engineering judgment, and a system-level perspective to deliver differentiated high-speed silicon solutions.

Responsibilities

• Lead the design and implementation of complex high-speed analog/mixed-signal circuits and critical SerDes IP.

• Define circuit approaches and design methodologies to achieve aggressive performance, power, area, and robustness objectives for 100G+ SerDes PHYs.

• Resolve the most challenging circuit-design issues through first-principles analysis, modeling, simulation, and silicon-based investigation.

• Lead technical reviews and influence decisions across architecture, analog/mixed-signal design, digital design, layout, physical design, and validation.

• Drive design closure across complex implementations, including post-layout verification, performance optimization, and silicon correlation.

• Identify opportunities for architectural innovation, design automation, and improved engineering efficiency.

• Contribute to technical roadmaps, project planning, and risk mitigation for next-generation SerDes products.

• Promote rigorous engineering practices, design quality, and knowledge sharing across the organization.

Qualifications:

• M.S. or Ph.D. in Electrical Engineering or a related field.

• Extensive experience in analog/mixed-signal IC design, 100G+ high-speed circuit design, or advanced semiconductor product development.

• Demonstrated record of successfully delivering complex circuit designs from architecture through implementation and silicon validation.

• Strong debugging skills and the ability to solve ambiguous, cross-disciplinary technical problems.

• Excellent technical communication skills and the ability to influence engineering decisions across teams.

Preferred Qualifications:

• Significant experience developing 100G+ high-speed SerDes or other high-performance analog/mixed-signal IP.

• Expertise in advanced CMOS process technologies and the associated challenges in circuit design, physical implementation, and variability.

• Proven expertise in one or more of the following technical areas:

• Fractional-N PLL, LC-VCO, DTC/TDC, multi-modulus divider (MMD).

• Phase interpolator, injection-locked oscillator, multi-phase clock generator.

• High-speed time-interleaved DAC and line driver.

• Transimpedance amplifier, CTLE, PGA, Cherry-Hooper amplifier, high-speed voltage followers.

• Time-interleaved SAR ADC, track-and-hold circuits.

• Bandgap, PTAT, LDO, temperature sensor, charge pump, auto-zero comparator, R2R DAC.

• Demonstrated success driving critical circuit blocks or subsystems to silicon with strong performance and quality.

• Experience influencing architecture and design methodology beyond an individual circuit block.

• Experience with circuit modeling, simulation automation, optimization, and silicon-to-model correlation.

• Patents, technical publications, or other evidence of meaningful technical innovation are a plus.

We are looking for technical leaders who can combine deep circuit-design expertise with architectural thinking and hands-on execution to solve the most challenging problems in next-generation high-speed connectivity.