SECTION I · THE BRIEF
Brief #23115Updated 16 OCT 2026BANGALORELever
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Design Verification Engineer - Bangalore

Designs ultra-low-power semiconductor IP that cuts AI compute power draw for data centers, robotics and other physical-AI systems.

Location
Bangalore
Company size
50–100
Posted
Today
Via
Lever
Section II · Full ProfileFree with an account
  • 01Comp band & equity packageLocked
  • 02Seniority & experience requirementsLocked
  • 03Interview process & rubricLocked
  • 04Hiring manager & team contextLocked
  • 05Growth trajectory in this roleLocked
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Design Verification Engineer - Bangalore

Velaura AI· BangaloreView company profile


Job title
Design Verification Engineer - Bangalore
Job location
Bangalore
Job description

Role Overview

We are looking for talented Design Verification Engineers to help verify and deliver Velaura’s next-generation Physical AI SoC. In this role, you will work closely with architects, RTL engineers, software engineers, and system teams to verify complex hardware blocks and system-level behavior across the entire platform.You will help establish confidence in the correctness, performance, reliability, and safety of the architecture—from individual RTL blocks to complete HW/SW systems running real-world workloads. We welcome engineers at all experience levels who enjoy understanding systems, finding corner cases, and solving challenging technical problems.

Responsibilities

● Develop and execute verification strategies for key portions of the Velaura SoC.

● Build verification environments using SystemVerilog, UVM, C/C++, assertions, formal verification, emulation, and related methodologies.

● Collaborate with architects and RTL engineers to define verification plans, coverage goals, and correctness criteria.

● Verify compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, and other critical SoC infrastructure.

● Perform HW/SW co-verification involving firmware, drivers, runtime software, and operating system interactions.

● Verify performance, latency, bandwidth, QoS, and real-time system behavior under representative workloads.

● Develop assertions, checkers, scoreboards, and automated verification infrastructure.

● Participate in emulation, FPGA prototyping, and pre-silicon software bring-up activities.

● Drive bug investigation, root-cause analysis, and debug across hardware and software boundaries.

● Post-silicon debug and root cause analysis.

● Leverage modern engineering tools, including AI-assisted verification workflows, to improve productivity, quality, and coverage.

● Contribute to a culture of technical excellence and continuous improvement.

Required Qualifications

● Experience verifying complex digital systems.

● Strong analytical and problem-solving skills.

● Strong understanding of computer architecture, microarchitecture, SoC architecture and digital design fundamentals.

● Experience with SystemVerilog, UVM, C/C++, assertions, coverage-driven verification, and related methodologies.

● Familiarity with formal verification techniques and tools.

● Understanding of memory systems, interconnect fabrics, caches, DMA engines, processors, or accelerator architectures.

● Experience debugging complex system-level issues.

● Ability to work effectively in a collaborative, multidisciplinary engineering environment.

Preferred Qualifications

● Experience with one or more of the following standards: ISO 26262, IEC 61508, IEC 61511, ISO 13849

● Experience with AI, machine learning, or edge AI hardware.

● Familiarity with robotics, drones, autonomous vehicles, or industrial automation systems.

● Experience verifying QoS, latency-sensitive, or real-time systems.

● Experience with HW/SW co-verification and system-level validation.

● Exposure to performance modeling, profiling, and workload characterization.

● Experience using modern AI tools and workflows to accelerate engineering productivity.

● Background in CPUs, GPUs, AI accelerators, networking and communications silicon, storage and data movement architectures, robotics and autonomous systems, automotive and ADAS platforms, aerospace and defense systems,
real-time and safety-critical computing, or functional safety architectures and methodologies.

Compensation & Benefits

At Velaura, we believe exceptional talent deserves exceptional rewards. Compensation for this role includes a base salary and very competitive equity compensation, allowing team members to share in the company’s long-term success.

The base pay listed represents a good faith estimate that the Company reasonably expects to pay for this position at the time of hire. Actual compensation will depend on multiple factors, including the candidate's skills, qualifications, relevant experience, and geographic location.

In addition to base salary and equity compensation, Velaura offers a comprehensive benefits package that may include medical, dental, and vision coverage; paid time off; flexible work arrangements; professional development opportunities; and other benefits designed to support the well-being and growth of our team.

Velaura is committed to pay equity and transparency and regularly benchmarks compensation to ensure we remain competitive in the market.

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Velaura AI headquarters

Company size

50–100 employees

Founded

2026

Total raised

$424,000,000

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Funding rounds