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Synthesis & Front-End STA Engineer - SpaceX

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Job Title
Synthesis & Front-End STA Engineer
Job Location
Irvine, CA, United States
Job Description

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.


As a member of our multifaceted ASIC implementation team, you will have the rare and phenomenal opportunity to craft upcoming SOCs that will enable our Starlink chips. These chips help connect, enable, and empower humanity every single day with performance that far surpasses that of traditional satellite internet and ground infrastructure limitations. Starlink delivers high-speed, low latency broadband internet to locations where access has been unreliable, expensive, or completely unavailable.

In this critical role, as a synthesis and front-end STA (static timing analysis) engineer, you will be collaborating with architecture, timing, and logic design teams to make a crucial impact on delivering cutting edge SOCs for customers on Earth and beyond. We are looking for people who want to dive in and get their hands dirty and push the limits of what is possible through innovation, determination, and teamwork.


  • Full chip and block level timing constraint development, consistent full chip and block constraint partitioning
  • Integrate DFT/BIST insertion flows into synthesis flow
  • Timing closure ownership throughout the entire project cycle (RTL, synthesis, and physical implementation)
  • Analysis of clock domain crossing paths at block and full chip level
  • Work with mixed signal IP/PLL/SerDes/PHY teams to drive integration, timing, logical equivalence checking and analysis of various IPs into RTL
  • Develop/modify/run RTL logic synthesis, formal verification, power intent verification and post synthesis timing validation flows
  • Execute low power design and physical synthesis, deploying knowledge of unified power format and power intent verification
  • Some logic design in Verilog/SystemVerilog and confirmation of quality of coding through LINT and clock domain crossing flows
  • Deploy and enhance methodology and flows related to timing constraint generation and verification and timing closure
  • Work closely with chip architecture, design verification, physical design, DFT, and power teams to achieve tapeout success on designs – generally bridging the RTL and place and route
  • Work with multi-disciplinary groups to make sure RTL/Netlists are on schedule and delivered with the highest quality by incorporating automated checks at every stage of the design process


  • Bachelor’s degree in electrical engineering, computer engineering or computer science
  • 3+ years of experience working as a synthesis and/or front-end STA engineer


  • Experience in ASIC multimode constraint generation, constraint partitioning and timing closure in advanced nodes
  • Knowledge of deep sub-micron FinFET technology nodes (7nm and below) timing challenges, multi-corner and multimode timing closure, process variations (AOCV, POCV based STA), voltage drop aware STA, and clock reconvergence pessimism removal
  • Hands-on experience in industry standard physical synthesis and STA tools (Synopsys DC, Primetime or equivalent)
  • Experience with clock domain crossings, DFT/Scan/MBIST/LBIST and understanding of their impact on synthesis, physical design and timing closure
  • Deep understanding of ASIC design flow, top-down and bottom-up design methodologies
  • Knowledge of low-power methodologies and leakage/dynamic power optimization flows and techniques
  • Familiar with implementation or integration of design blocks using Verilog/SystemVerilog
  • Experience with high reliability design and implementations
  • Excellent scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.)
  • Self-driven individual with a can-do attitude, and an ability to work in a dynamic group environment


  • Must be willing to travel when needed (typically <10%)
  • Willing to work extended hours and weekends to meet critical deadlines, as needed

Pay range:    
Synthesis and Front-End STA Engineer/Level I: $120,000.00 - $145,000.00/per year    
Synthesis and Front-End STA Engineer/Level II: $140,000.00 - $170,000.00/per year    

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.  


  • To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR) you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.  

SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

Applicants wishing to view a copy of SpaceX’s Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should notify the Human Resources Department at (310) 363-6000.

SpaceX Headquarters Location

Hawthorne, CA

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SpaceX Company Size

Between 10,000 - 20,000 employees

SpaceX Founded Year


SpaceX Total Amount Raised


SpaceX Funding Rounds

View funding details
  • Private Equity

    $250,000,000 USD

  • Series Unknown

    $1,724,965,480 USD

  • Grant

    $69,950,000 USD

  • Series Unknown

    $337,355,200 USD

  • Secondary Market

    $755,000,000 USD

  • Grant

    $14,470,000 USD

  • Series Unknown

    $850,000,000 USD

  • Undisclosed

    $1,900,000,000 USD

  • Series Unknown

    $346,200,000 USD

  • Grant

    $3,000,000 USD

  • Undisclosed

    $535,744,188 USD

  • Series J

    $486,198,978 USD

  • Debt Financing

    $250,000,000 USD

  • Series I

    $214,000,000 USD

  • Series H

    $100,000,000 USD

  • Series H

    $351,000,000 USD

  • Series G

    $1,000,000,000 USD

  • Secondary Market

    $30,000,000 USD

  • Series F

    $50,000,000 USD

  • Series E

    $30,435,000 USD

  • Series E

    $15,025,000 USD

  • Series D

    $29,000,000 USD

  • Series C

    $32,000,000 USD

  • Series B

    $11,000,000 USD

  • Series A

    $61,000,000 USD