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Signal and Power Integrity Hardware Engineer - Astera Labs

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Job Title
Signal and Power Integrity Hardware Engineer
Job Location
Santa Clara, CA
Job Description

Astera Labs Inc., a semiconductor company headquartered in the heart of California’s Silicon Valley, is a leader in purpose-built connectivity solutions for data-centric systems throughout the data center. Partnering with leading processor vendors, cloud service providers, seasoned investors, and world-class manufacturing companies, Astera Labs is helping customers remove performance bottlenecks in data-intensive systems that are limiting the true potential of applications such as artificial intelligence and machine learning. The company’s product portfolio includes system-aware semiconductor integrated circuits, boards, and services to enable robust CXL, PCIe, and Ethernet connectivity.

Job Description:

As an Astera SI/PI Hardware Engineer you will be part of a team that designs and supports Astera Labs’ portfolio
of connectivity products in the world’s leading cloud service providers and server and network OEMs. In this
role, you will need develop stack-ups, via structures, and trace geometries to execute on SI/PI engineering,
qualification, initial ramp, and high-volume production, with the opportunity to build a laboratory and
simulation flow.

Basic qualifications:

  • Strong academic/technical background in electrical engineering; Bachelor’s is required; Master’s preferred
  • 5+ years of hands-on high-speed SI/PI design, simulation, and measurement experience
  • Proven track record with defining hardware system constraints and high-speed technology roadmaps
  • Cross-functional design mentality with silicon design community to develop systems
  • Self-starting, professional, and hands-on work ethic that can execute intense research in a dynamic
  • Authorized to work in the US and start immediately

Required experience:

  • Familiar with SI and PI design challenges for high-speed interconnects
  • Hardware product design experience in networking, compute, or RF
  • 2D and 3D simulation experience with Cadence/Mentor/Ansys/ADS/etc. toolsets
  • EM modelling of connector structures
  • High-speed SERDES measurement, channel simulation, and equalization
  • Expertise in DDR4/5 memory bus designs
  • Expertise in multi-level and NRZ signaling, COM, BER, jitter analysis
  • Familiar with VNA, TDR, real-time and sub-sampling oscilloscopes, etc.
  • Working knowledge of PCB fabrication limits and trade-offs
  • PI experience a bonus
  • Familiar with industry standard such as IEEE802.3

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs Headquarters Location

Santa Clara, CA

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Astera Labs Company Size

Between 100 - 500 employees

Astera Labs Founded Year


Astera Labs Total Amount Raised


Astera Labs Funding Rounds

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  • Series D

    $150,000,000 USD

  • Series C

    $50,000,000 USD

  • Series Unknown

    $6,350,000 USD