Signal and Power Integrity Hardware Engineer - Astera Labs

Job Description:

As an Astera SI/PI Hardware Engineer you will be part of a team that designs and supports Astera Labs’ portfolio
of connectivity products in the world’s leading cloud service providers and server and network OEMs. In this
role, you will need develop stack-ups, via structures, and trace geometries to execute on SI/PI engineering,
qualification, initial ramp, and high-volume production, with the opportunity to build a laboratory and
simulation flow.

Basic qualifications:

• Strong academic/technical background in electrical engineering; Bachelor’s is required; Master’s preferred
• 5+ years of hands-on high-speed SI/PI design, simulation, and measurement experience
• Proven track record with defining hardware system constraints and high-speed technology roadmaps
• Cross-functional design mentality with silicon design community to develop systems
• Self-starting, professional, and hands-on work ethic that can execute intense research in a dynamic
  environment
• Authorized to work in the US and start immediately

Required experience:

• Familiar with SI and PI design challenges for high-speed interconnects
• Hardware product design experience in networking, compute, or RF
• 2D and 3D simulation experience with Cadence/Mentor/Ansys/ADS/etc. toolsets
• EM modelling of connector structures
• High-speed SERDES measurement, channel simulation, and equalization
• Expertise in DDR4/5 memory bus designs
• Expertise in multi-level and NRZ signaling, COM, BER, jitter analysis
• Familiar with VNA, TDR, real-time and sub-sampling oscilloscopes, etc.
• Working knowledge of PCB fabrication limits and trade-offs
• PI experience a bonus
• Familiar with industry standard such as IEEE802.3