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Senior Validation Engineer (Memory Validation) - Astera Labs

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Job Title
Senior Validation Engineer (Memory Validation)
Job Location
Santa Clara, CA
Job Description

Astera Labs Inc., a semiconductor company headquartered in the heart of California’s Silicon Valley, is a leader in purpose-built connectivity solutions for data-centric systems throughout the data center. Partnering with leading processor vendors, cloud service providers, seasoned investors, and world-class manufacturing companies, Astera Labs is helping customers remove performance bottlenecks in data-intensive systems that are limiting the true potential of applications such as artificial intelligence and machine learning. The company’s product portfolio includes system-aware semiconductor integrated circuits, boards, and services to enable robust CXL, PCIe, and Ethernet connectivity.

Job Responsibilities:

The mission of this role is to validate all aspects of the memory subsystems on the ASIC and its systems using advanced high-speed test equipment and scalable automation platforms. This would include electrical validation of memory interfaces like DDR and validation of vendor memories for inter-operability. The validation team holds customers’ system requirements in the highest regard and is solely responsible for certifying a product’s conformance to this high bar. As a memory validation engineer your responsibilities would include:

  • Creating memory validation test plans.
  • Using platform level tools and techniques to ensure performance to memory specifications.
  • Executing of DDR memory stress tests in system and debug of failures.
  • Interfacing with Architecture, Design, and Validation teams to review and address debug results.
  • Developing software tools to support silicon bring-up of the memory subsystem, implementing special memory tests.
  • Silicon early bring-up, investigating system DRAM issues and discovering workarounds.

Basic qualifications:

  • Bachelor’s in Electrical Engineering or Computer Science is required, and a Master’s is preferred.
  • 5+ years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
  • Deep understanding of DDR technologies such as DDR, LPDDR, JEDEC standards.
  • Experienced with implementing DRAM/memory controller initialization code, memory subsystem/DDR PHYs training/calibration software.
  • Experience and interested in writing code to test IO devices and/or functional IP units.
  • Familiarity with: boot code, computer system initialization, device drivers, SoC bring up, IO devices, debuggers, analysis tools (logic analyzers, oscilloscopes)
  • Developing/executing test plan for pre and post silicon verification, designing and crafting targeted tests for validating specific memory controller functionality/ECOs.
  • A strong background in bench automation techniques, especially Python.

Required experience:

  • Experience defining validation plans for functional, signal and power integrity work HW and ASIC teams to debug complex memory issues.
  • Experience in system testing, characterization and compliance, margin analysis and optimization.
  • Experience working with memory vendors to identify issues, working with SOC to improve memory calibration and tuning sequences.
  • Experience developing automation scripts and test tools for execution efficiency, repeatability, and reporting.
  • Familiarity with memory standards and compliance testing.
  • Comfortable using high speed oscilloscopes, logical analyzers, memory interposers.

Preferred experience:

  • Extensive experience with memory debug techniques and methodologies
  • Direct experience working on enterprise grade memory subsystem validation, diagnostics and tuning.
  • Experience with DRAM memory vendors on DDR4 or DDR5.
  • Experience with firmware-based operations of high-speed memory sub-systems, configurations of DRAM based memories.
  • Good knowledge of SoC package, board design and related signal integrity.
  • Basic understanding of x86/ARM architecture, UEFI/Linux boot sequence.
  • Previous experience working with major DRAM memory vendors and validation of DRAM device is also a plus.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs Headquarters Location

Santa Clara, CA

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Astera Labs Company Size

Between 100 - 500 employees

Astera Labs Founded Year


Astera Labs Total Amount Raised


Astera Labs Funding Rounds

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  • Series D

    $150,000,000 USD

  • Series C

    $50,000,000 USD

  • Series Unknown

    $6,350,000 USD