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Senior ATE Test Engineer - Astera Labs

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Job Title
Senior ATE Test Engineer
Job Location
Santa Clara, CA
Job Description

Astera Labs is a global leader delivering semiconductor-based connectivity solutions purpose-built to unleash the full potential of intelligent data infrastructure at cloud-scale. Our class-defining first-to-market products based on PCIe, CXL, and Ethernet technologies deliver critical connectivity for high-value artificial intelligence and machine learning applications. Our focus on customer-driven product definition and commitment to design solutions in the cloud, for the cloud, results in breakthrough execution and scale for our customers. We are headquartered in the heart of California’s Silicon Valley, with R&D centers and offices in Taiwan, China, Vancouver and Toronto, Canada, and Haifa, Israel.

Job Description

We are looking for Senior ATE Test Engineers with proven experience in developing and supporting complex mixed-signal silicon SoC products. The ideal candidate will develop and oversee SoC test strategy, interact with manufacturing partners, define, and implement ATE programs and own the product from design, initial samples all the way through high volume production ramp. The candidate should have working knowledge of communication/interface protocols such as PCI-Express (Gen-4/5), Ethernet, Infiniband, DDR, NVMe, USB, etc.

Basic Qualifications

  • Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, and a Master’s is preferred.
  • ≥5-year experience releasing complex SoC/silicon products to high volume manufacturing.
  • Working knowledge of high-speed protocols like PCIe, Ethernet, Infiniband, DDR, NVMe, USB, etc.
  • Professional attitude with ability to execute on multiple tasks with minimal supervision.
  • Strong team player with good communication skills to work alongside a team of high caliber engineers.
  • Entrepreneurial, open-mind behavior and can-do attitude.

Required Experience

  • Hands-on experience with high-speed mixed signal SoC test program/hardware development on multiple high-speed test platforms.
  • Collaboration with design team to define test strategy, create and own test plan.
  • Tester platform selection, design, and development of ATE hardware for wafer sort and final test.
  • Familiar with high-speed load board design techniques.
  • Proven track record of implementing ATE patterns to optimize tester resources and minimize ATE test time while maintaining product quality.
  • Strong knowledge and development of DFT techniques implemented in silicon that provide maximum defect and parametric device coverage – SCAN, MEMBIST, SerDes and other functional tests.
  • Skilled in control interfaces – I2C, I3C, SPI, MDIO, JTAG etc.
  • Expertise in production test of high speed SerDes operating at 16Gbps and higher.
  • Skilled in ATE programming, silicon/ATE bring-up, bench-ATE correlation and debug.
  • Experience with lab equipment including protocol analyzers and oscilloscopes.
  • Experience with using Advantest 93k ATE platform.
  • Proficiency in, at least, one modern programming language such as C/C++, Python.

Preferred experience

  • Fluent in data processing using high level programming languages.
  • Familiarity with modern databases.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

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Astera Labs Headquarters Location

Santa Clara, CA

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Astera Labs Company Size

Between 100 - 500 employees

Astera Labs Founded Year


Astera Labs Total Amount Raised


Astera Labs Funding Rounds

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  • Series D

    $150,000,000 USD

  • Series C

    $50,000,000 USD

  • Series Unknown

    $6,350,000 USD

Astera Labs' Tech Stack

Astera Labs' Investors