Principal Formal Verification Engineer - Astera Labs

Basic Qualifications:

• Bachelor’s degree in Electrical Engineering (EE) is required; a Master’s or PhD in EE is preferred. Additional background in Math or Computer Science is highly desirable.
• 5+ years of experience in formal verification or 7+ years of experience in traditional design verification (DV).
• Strong professional work ethic with the ability to manage and prioritize multiple tasks in a dynamic environment.
• Proven ability to plan and prepare for customer meetings and to work with minimal supervision.
• Entrepreneurial mindset with a proactive, customer-focused attitude. Ability to think and act quickly while maintaining a high standard of quality.
• Strong cross-functional collaboration skills.

Required Experience:

• Develop detailed formal verification (FV) test plans based on design specifications and collaborate with design teams to refine micro-architecture specifications.
• Identify key logic components and critical micro-architectural properties essential for ensuring design correctness.
• Implement formal verification models, abstractions, assertions, and utilize assertion-based model checking to detect corner-case bugs.
• Apply complexity reduction techniques using industry-standard EDA tools or academic formal verification tools to achieve proof convergence or sufficient depth.
• Develop and maintain scripts to enhance FV productivity and streamline verification processes.
• Assist design teams with the implementation of assertions and formal verification testbenches for RTL at unit/block levels.
• Participate in design reviews and collaborate with design teams to optimize design quality and performance, power, area (PPA) metrics based on formal analysis feedback.
• Strong proficiency in System Verilog/Verilog.
• Good scripting abilities with Python or Perl.

Preferred Experience:

• Hands-on experience with formal verification tools such as Synopsys VCFormal and Cadence JasperGold.
• Experience with both bug hunting and static proof verification techniques.
• Familiarity with automating formal verification workflows within a CI/CD environment.