ATE Test Engineering Manager - Astera Labs

We are looking for an ATE Test Engineering Manager with proven experience in managing a team of highly experienced test engineers while supporting the development of complex mixed-signal silicon SoC products. The candidate will lead the ATE engineering team, managing ATE development for new products, meeting existing KPIs  and developing internal processes to scale with the increasing number of products. Roles include managing NPI product releases and overseeing the SoC test strategy. The candidate should have working knowledge of communication/interface protocols such as PCI-Express (Gen-4/5), Ethernet, Infiniband, DDR, NVMe, USB, etc.

Basic qualifications:

• Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, and a Master’s is preferred.
• ≥5-year experience leading a highly functioning ATE product development team
• ≥8-year experience releasing complex SoC/silicon products to high volume manufacturing.
• Working knowledge of high-speed protocols like PCIe, Ethernet, Infiniband, DDR, NVMe, USB, etc.
• Professional attitude with ability to execute on multiple tasks with minimal supervision. 
• Strong team player with good communication skills to work alongside a team of high caliber engineers.
• Entrepreneurial, open-mind behavior and can-do attitude.

Required experience:

• Proven track record leading ATE teams to successfully deliver SoC ATE solutions meeting the cost and timeframe goals.
• Collaboration with design team to define test strategy, create and own test plan.
• Tester platform selection, design and development of ATE hardware for wafer sort and final test.
• Familiar with high speed load board design and simulation techniques.
• Proven track record of implementing ATE patterns to optimize tester resources and minimize ATE test time while maintaining product quality.
• Strong knowledge and development of DFT techniques implemented in silicon that provide maximum defect and parametric device coverage – SCAN, MEMBIST, SerDes and other functional tests.
• Expertise in production test of high speed SerDes operating at 16Gbps and higher.
• Skilled in ATE programming, silicon/ATE bring-up, bench-ATE correlation and debug.

Preferred experience:

• Fluent in data processing using high level programming languages.
• Familiarity with modern databases.