ASIC Design Engineer - CCU at Groq

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Groq

(58 open jobs)

Groq is a machine learning systems company building easy to use, high TOPS/Watt accelerators with sub-millisecond latency.


Job title
ASIC Design Engineer - CCU
Job listing last updated at
Jul 1, 2021
Job listing location
Mountain View, CA
Job listing source
greenhouse
Job listing link
External link
Bay Area company location:

Job description

Groq is a machine learning systems company building easy-to-use solutions for accelerating artificial intelligence workloads. Our work spans hardware, software, and machine learning technology. We are seeking an exceptional Sr. ASIC Design Engineer to join our team.

The Sr ASIC Design Engineer will work closely with internal interdisciplinary teams to help us build high-performance, power efficient chips for AI applications. You must be responsive, flexible and able to succeed within an open collaborative peer environment.

ESSENTIAL DUTIES AND RESPONSIBILITIES:

  • Responsible for the architecture, micro-architecture and design of the chip control unit of our Machine Learning ASICs
  • Ownership of the top-level netlist, selection and integration of IP,  CDC, clocking, resets.
  • Architect, implement and verify  power management techniques, multiple voltage domains, isolation cells insertion.
  • Architect and implement security solutions
  • Collaborate with system software team on boot code and firmware development
  • Guide and review verification of blocks owned
  • Participate in silicon bring-up for blocks owned
  • Coordinate design activities for block with Software and Systems teams

QUALIFICATIONS:

  • BS in Electrical Engineering or Computer Engineer or related degree required; advanced degrees (MS, PhD) a plus. 
  • Expert level knowledge in control and boot subsystems  of complex, high performance processors, GPU’s or application processors
  • Expert in microcontroller peripherals including I2C/SMB, SPI, UART, ADC 
  • Experience with multiple clock domains and asynchronous interfaces
  • Expert knowledge in clock and reset design, and implementation of complex ASIC power management systems with UPF
  • 6+ years of meaningful industry experience and a background in high­ speed complex ASIC/SOC design
  • Experience with all stages in the ASIC design flow including emulation, prototyping, DFT, Synthesis, timing analysis, floorplanning, ECO, bringup & lab debug, and ATE test development 
  • Experience in integrating ASIC IP into SOC
  • Experience in Security and BootLoaders a plus
  • Experience with industry standard EDA tools from Cadence, Synopsys or Mentor
  • Expertise in developing firmware and system management software for high performance processors a plus
  • Experience in designing tools and scripts for creating control and status register maps a plus
  • Proficient coding skills in Verilog or SystemVerilog

PERSONAL ATTRIBUTES:

  • Ability to build strong relationships
  • Good written and oral communication skills; strong technical documentation skills
  • Good interpersonal skills
  • Highly self-motivated and directed; self-confidence and self-starter
  • Keen attention to detail
  • Proven analytical and problem-solving abilities
  • Ability to effectively prioritize and execute tasks in a high-pressure environment
  • Experience working in a team-oriented, collaborative environment

Groq is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.

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